In semiconductor manufacturing process, trenches are often etched on the wafer. In some special application field, semiconductor devices of the integrated circuit need to etch deep silicon trenches. Deep silicon trench etching (DSIE) process is used to etch deep silicon trenches. In the DSIE process, the wafer is used as a substrate, a photoresist is used as a mask layer, patterns can be transferred on the wafer, and some special functions can be achieved.
In a conventional DSIE process, as the DSIE process time is long, an etching depth is large (the etching depth can be several hundred micrometers), and the DSIE process is limited by the thickness of the photoresist, after deep silicon trenches are etched, resist reticulation will be formed on the wafer, part of the photoresist will be completely etched away on the wafer. The above phenomena will lead to problems such as patterns of the wafer are not complete, sizes are irregular and have large errors, the photoresist on a surface of the wafer after the DSIE process is difficult to remove. Meanwhile, the photoresist is not protected enough, a DSIE etching depth is limited, which cannot meet requirements of more manufacturing process. The problem of resist reticulation on the wafer after DSIE process has become a development bottleneck of the manufacturing process.
In order to overcome problems such as resist reticulation on the wafer in the DSIE process, patterns are not complete after the DSIE process, photoresists on the wafer surface are difficult to remove. SiO2 or SiN is proposed as an etching mask layer to replace the photoresist in the art to avoid problems caused by using the photoresist as the mask layer. However, using SiO2 or SiN as the etching mask layer cannot solve the problem of resist reticulation on the wafer surface caused by using the photoresist as the mask layer essentially, and also new problems are aroused. When SiO2 or SiN is used as the mask layer, SiO2 and SiN cannot be removed completely after the DSIE process, there will be fragments on the wafer surface, which further limits a wide use of the DSIE process.